At the SPIE Advanced Lithography conference in San Jose, Calif. (USA), world-leading research and innovation hub in nano-electronics and digital technologies imec and its partners will present a patterning solution for a 42 nm-pitch M1 layer and a 32 nm-pitch M2 layer in logic design compatible with the foundry N5 requirements. The approach includes two scenarios for EUVL insertion that, when combined with an array of scaling boosters, serve as a basis of the industry requirements for power, performance, area and cost.
Including proposals for design rules, masks, photoresists, etching, and metrology and an extensive process variation assessment, imec’s R&D has established the first comprehensive solution for EUVL enablement in high-volume manufacturing.
As an alternative to the cost-prohibitive and complex self-aligned quadruple patterning (SAQP) + immersion triple block patterning for the 32nm metal layer (M2), imec has developed two approaches that include exposure on ASML’s NXE:3300B EUV-scanner. The primary solution involves completing the SAQP with a single EUV blocking step, which offers a 20 percent wafer cost reduction over the full immersion approach. The alternate approach relies on EUV for a single patterning step, replacing both the SAQP and triple blocking steps. This adds an additional cost reduction, but has more implementation challenges than the SAQP+EUV block solution. As pitch-only scaling becomes a burden in technology node transition, imec’s solutions have been complemented by co-optimizing the technology and the design libraries resulting in significantly lower area while lessening the burden in pitch-only scaling. This allows a full node definition with fixed wafer cost increase with more area reduction.
As part of the solution, imec and ASML created a 2D OPC full-chip model, which was then used to design and fabricate the EUVL block mask. Also for the etch process, solutions have been found that meet the requirements. As for the mask pellicles, imec reports on work for 250W exposure membranes, investigating a promising group of materials based on carbon nanotubes (CNT).
Lastly, the SAQP and block structures have been characterized in detailed morphological studies, assessing pattern fidelity and variability. At a 32nm pitch, even minor process variations in EUVL may have significant impact on device performance. Such variations are due to overlay and critical dimension uniformity issues, in addition to EUVL-specific effects such as shadowing, M3D, flare and stochastic effects. Imec simulated and measured these effect on the wafers, demonstrating the suitability of the proposed solutions and identifying approaches to fine-tune processing computationally, e.g. further refining the OPC.