Double debut from Intel

Double debut from Intel »

Intel claimed a 2x density advantage over rival chip makers when it announced details of its new 10 nm devices along with a new 22 nm FinFET foundry service in San Francisco on 28 March.


Intel used its Manufacturing Day event in San Francisco to unveil new 10nm chips scheduled to enter production in the latter half of 2017. Intel’s new processors will pack 100.8 million transistors into one square millimeter, nearly double the density of rival chip makers’ 10 nm devices, Intel said.

In making the 10 nm announcement, Intel quelled speculation over whether its latest chips would enter production this year. Intel’s road map calls for its newest devices to enter the market almost three years after it debuted its previous generation 14 nm chips.

Intel also announced it would use a different metric to gauge performance of next-generation devices, challenging peer manufacturers to utilize the same guide when discussing performance of their own semiconductor devices. The Intel metric averages density of a small and large logic cell; its 10nm chips utilise a two-input NAND cell with two active gates and a scan ‘flip-flop’ cell with as many as 25 active gates.

Intel representatives said their latest design will have more than 100 million transistors per square millimeter, while it believes rivals Samsung and TSMC pack about half that many transistors into the same space. Intel senior fellow and director of process architecture Mark Bohr said he believed Intel competitors previously used a similar metric in describing the capabilities of their own chips, but discontinued doing so when it appeared that performance was not increasing as fast as it had previously.


Intel said it continues to lead in transistor design, providing a full generation of improved performance, power, density and cost-per-transistor reduction when compared with others. (Credit: Intel Corporation)

Intel’s new 10 nm chips (Cannonlake devices) and subsequent generations will follow a three-year cadence. While the company previously had 18- to 24-month gaps between generations, the challenges of developing greater densities while keeping costs low and also increasing performance has forced chip makers to depend on multi-pattern lithography and other enhancements that take more time than shrinking device features alone, which was the common pathway to creating faster, denser transistor cores at previous nodes. Intel forecast another three year gap before its next new node is released; it plans to introduce performance enhancements for 10nm devices as interim steps between nodes, referring to those generations as 10+ and 10++.

Intel’s new 10 nm chip utilizes the tightest gate and metal pitches found in semiconductor manufacturing, it said, adding that this new generation marks industry’s first high volume use of self-aligned quad patterning. To compensate for the rising costs of more lithographic steps, Intel said it utilizes a contact over active gate (COAG) design that helps deliver 10 percent greater transistor density. The use of a single dummy gate in its architecture rather than two provides additional scaling advantages that help reduce costs, Intel said.

The company also announced its 22 nm node FinFET low-power foundry process designed to compete for business will fully depleted silicon-on-insulator (FD-SOI) processes, such as those offered by competitors including Globalfoundries. Intel expects to ramp its 22 nm FFL process before the end of 2017; the new devices target similar types of applications that FD-SOI now supports including mobile end user products and Internet of Things (IoT) devices. Process design kits (PDKs) are in pre-release with full 1.0 versions expected by 1 June 2017.

Speaking about its new FinFET foundry services, Intel said it includes both high-performance and low power transistors with substantially less leakage than competing chip makers’ processes offer at the 28 nm node. The company said it plans to provide more cost-competitive solutions than rivals through simplified design rules and interconnects as well as 14 nm-like FinFETs. A company spokesman also said that Intel believes its 22 nm FinFET process will be easier to use than competing solutions. The company plans to price the new FinFET process very competitively to support aggressive revenue targets.

 

Intel details the performance of previous-generation devices, saying it offers the world's top performing transistors. (Credit: Intel Corporation)

 

Additional Intel graphics and information supporting its new product releases can be found here: https://newsroom.intel.com/press-kits/leading-edge-intel-technology-manufacturing/#infographics

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